View LTC3830_426733.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC3830/LTC3830-1 High Power Step-Down Synchronous DC/DC Controllers for Low Voltage Operation
FEATURES
s s s s s s
DESCRIPTIO
s s s
s s s s s
High Power Switching Regulator Controller for 3.3V-5V to 1.xV-3.xV Step-Down Applications No Current Sense Resistor Required Low Input Supply Voltage Range: 3V to 8V Maximum Duty Cycle > 91% Over Temperature All N-Channel External MOSFETs Excellent Output Regulation: 1% Over Line, Load and Temperature Variations High Efficiency: Over 95% Possible Adjustable or Fixed 3.3V Output (16-Pin Version) Programmable Fixed Frequency Operation: 100kHz to 500kHz External Clock Synchronization Soft-Start (Some Versions) Low Shutdown Current: <10A Overtemperature Protection Available in S8, S16 and SSOP-16 Packages
The LTC(R)3830/LTC3830-1 are high power, high efficiency switching regulator controllers optimized for 3.3V-5V to 1.xV-3.xV step-down applications. A precision internal reference and feedback system provide 1% output regulation over temperature, load current and line voltage variations. The LTC3830/LTC3830-1 use a synchronous switching architecture with N-channel MOSFETs. Additionally, the chip senses output current through the drain-source resistance of the upper N-channel FET, providing an adjustable current limit without a current sense resistor. The LTC3830/LTC3830-1 operate with an input supply voltage as low as 3V and with a maximum duty cycle of >91% over temperature. They include a fixed frequency PWM oscillator for low output ripple operation. The 200kHz free-running clock frequency can be externally adjusted or synchronized with an external signal from 100kHz to 500kHz. In shutdown mode, the LTC3830 supply current drops to <10A. The LTC3830-1 differs from the LTC3830 S8 version by replacing shutdown with a soft-start function. For a similar, pin compatible DC/DC converter with an output voltage as low as 0.6V, please refer to the LTC3832.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s
CPU Power Supplies Multiple Logic Supply Generator Distributed Power Applications High Efficiency Power Conversion
TYPICAL APPLICATIO
4.7F
VIN 3V TO 8V 5.1
+
0.1F 0.01F 15k GND PVCC1 12.7k 1% FB 5.36k 1% 3.3nF L: SUMIDA CDEP105-3R2MC-88 COUT: PANASONIC EEFUEOD271R G2 4.7F LTC3830-1 PVCC2 SS COMP G1 12V
100
220F 10V
90 80 70 60 50 40 0 1 2 34567 LOAD CURRENT (A)
M1 Si7806DN
L 3.2H 1.8V 9A
M2 Si7806DN
B320A
+
COUT 270F 2V
3830 F01
EFFICIENCY (%)
Figure 1. High Efficiency 3V-8V to 1.8V Power Converter
U
Efficiency
VIN = 3.3V VOUT = 1.8V 8 9 10
3830 TA02
U
U
sn3830 3830fs
1
LTC3830/LTC3830-1
ABSOLUTE AXI U RATI GS
Supply Voltage VCC ....................................................................... 9V PVCC1,2 ................................................................ 14V Input Voltage IFB, IMAX ............................................... - 0.3V to 14V SENSE+, SENSE-, FB, SHDN, FREQSET ....................... - 0.3V to VCC + 0.3V
PACKAGE/ORDER I FOR ATIO
TOP VIEW G1 1 PVCC1 2 GND 3 FB 4 8 7 6 5 G2 VCC/PVCC2 COMP SHDN
ORDER PART NUMBER LTC3830ES8
G1 1 2 3 4 5 6 7 8 TOP VIEW 16 G2 15 PVCC2 14 VCC 13 IFB 12 IMAX 11 FREQSET 10 COMP 9 SS
S8 PACKAGE 8-LEAD PLASTIC SO
S8 PART MARKING 3830 ORDER PART NUMBER LTC3830-1ES8 S8 PART MARKING 38301
TJMAX = 125C, JA = 130C/ W
TOP VIEW G1 1 PVCC1 2 GND 3 FB 4 8 7 6 5 G2 VCC/PVCC2 COMP SS
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 130C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC, PVCC1, PVCC2 = 5V, unless otherwise noted. (Note 2)
SYMBOL VCC PVCC VUVLO VFB VOUT VOUT PARAMETER Supply Voltage PVCC1, PVCC2 Voltage Undervoltage Lockout Voltage Feedback Voltage Output Voltage Output Load Regulation Output Line Regulation VCOMP = 1.25V
q
ELECTRICAL CHARACTERISTICS
CONDITIONS
q
(Note 7)
VCOMP = 1.25V
q
IOUT = 0A to 10A (Note 6) VCC = 4.75V to 5.25V
2
U
U
W
WW
U
W
(Note 1)
Junction Temperature ........................................... 125C Operating Temperature Range (Note 9) .. - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC3830EGN LTC3830ES GN PART MARKING 3830
PVCC1 PGND GND SENSE- FB SENSE+ SHDN
GN PACKAGE S PACKAGE 16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO
TJMAX = 125C, JA = 130C/ W (GN) TJMAX = 125C, JA = 100C/ W (S)
MIN 3 3
q
TYP 5 2.4
MAX 8 13.2 2.9 1.275 1.278 3.350 3.365
UNITS V V V V V V V mV mV
sn3830 3830fs
1.255 1.252 3.250 3.235
1.265 1.265 3.3 3.3 2 0.1
LTC3830/LTC3830-1
The q denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC, PVCC1, PVCC2 = 5V, unless otherwise noted. (Note 2)
SYMBOL IVCC IPVCC fOSC VSAWL VSAWH VCOMPMAX AV gm ICOMP IMAX PARAMETER Supply Current PVCC Supply Current Internal Oscillator Frequency VCOMP at Minimum Duty Cycle VCOMP at Maximum Duty Cycle Maximum VCOMP Error Amplifier Open-Loop DC Gain Error Amplifier Transconductance Error Amplifier Output Sink/Source Current IMAX Sink Current IMAX Sink Current Tempco VIH VIL IIN ISS ISSIL RSENSE RSENSEFB tr, tf tNOV DCMAX SHDN Input High Voltage SHDN Input Low Voltage SHDN Input Current Soft-Start Source Current Maximum Soft-Start Sink Current In Current Limit SENSE Input Resistance SENSE to FB Resistance Driver Rise/Fall Time Driver Nonoverlap Time Maximum G1 Duty Cycle Figure 2, PVCC1 = PVCC2 = 5V (Note 5) Figure 2, PVCC1 = PVCC2 = 5V (Note 5) Figure 2, VFB = 0V (Note 5), PVCC1 = 8V
q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS Figure 2, VSHDN = VCC VSHDN = 0V Figure 2, VSHDN = VCC (Note 3) VSHDN = 0V FREQSET Floating
q q q q q
MIN
TYP 0.7 1 14 0.1
MAX 1.6 10 20 10 250
UNITS mA A mA A kHz V V V kHz/A dB
160
200 1.2 2.2
VFB = 0V, PVCC1 = 8V Measured from FB to COMP, SENSE + and SENSE - Floating, (Note 4) Measured from FB to COMP, SENSE + and SENSE - Floating, (Note 4) VIMAX = VCC (Note 10) VIMAX = VCC (Note 6)
q q q q
2.85 10 46 520 55 650 100
q
fOSC/IFREQSET Frequency Adjustment
780
mho A
9 4 2.4
12 12 3300
15 20
A A ppm/C V
0.8 0.1 -8 -12 1.6 29.2 18 80 25 91 120 95 250 250 1 -16
V A A mA k k ns ns %
VSHDN = VCC VSS = 0V, VIMAX = 0V, VIFB = VCC VIMAX = VCC, VIFB = 0V, VSS = VCC (Note 8), PVCC1 = 8V
q q
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 3: Supply current in normal operation is dominated by the current needed to charge and discharge the external FET gates. This will vary with the LTC3830 operating frequency, operating voltage and the external FETs used. Note 4: The open-loop DC gain and transconductance from the SENSE+ and SENSE - pins to COMP pin will be (AV)(1.265/3.3) and (gm)(1.265/3.3) respectively. Note 5: Rise and fall times are measured using 10% and 90% levels. Duty cycle and nonoverlap times are measured using 50% levels. Note 6: Guaranteed by design, not subject to test.
Note 7: PVCC1 must be higher than VCC by at least 2.5V for the current limit protection circuit to be active. Note 8: The current limiting amplifier can sink but cannot source current. Under normal (not current limited) operation, the output current will be zero. Note 9: The LTC3830E/LTC3830-1E are guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 10: The minimum and maximum limits for IMAX over temperature includes the intentional temperature coefficient of 3300ppm/C. This induced temperature coefficient counteracts the typical temperature coefficient of the external power MOSFET on-resistance. This results in a relatively flat current limit over temperature for the application.
sn3830 3830fs
3
LTC3830/LTC3830-1 TYPICAL PERFOR A CE CHARACTERISTICS
Load Regulation
3.34 3.33 3.32 TA = 25C REFER TO FIGURE 12 1.275 1.273 1.271 1.269
ERROR AMPLIFIER TRANSCONDUCTANCE (mho)
VOUT (V)
3.31 3.30 3.29 3.28 3.27 3.26 -15 -10 5 0 OUTPUT CURRENT (A) -5 10 15
3830 G02
VFB (V)
Output Voltage Temperature Drift
ERROR AMPLIFIER SINK/SOURCE CURRENT (A)
3.34 3.33 3.32
VOUT (V)
30 20 10 0 -10 -20 -30
VOUT (mV)
180 160 140 120 100 80 60 40 -50 -25 0 75 50 25 TEMPERATURE (C) 100 125
ERROR AMPLIFIER OPEN-LOOP GAIN (dB)
REFER TO FIGURE 12 OUTPUT = NO LOAD
3.31 3.30 3.29 3.28 3.27 3.26 -50 -25 0 75 50 25 TEMPERATURE (C) 100
Oscillator Frequency vs Temperature
250 240
OSCILLATOR FREQUENCY (kHz) OSCILLATOR FREQUENCY (kHz) 600
FREQSET FLOATING
500 400 300 200 100 0 -40
230 220 210 200 190 180 170 160 -50 -25 0 25 75 50 TEMPERATURE (C) 100 125
VSAWH - VSAWL (V)
4
UW
3830 G04 3831 G08
Line Regulation
TA = 25C 10 8 6 4 800 750 700 650 600 550
Error Amplifier Transconductance vs Temperature
VFB (mV)
1.267 1.265 1.263 1.261 1.259 1.257 1.255 3 4 6 7 5 SUPPLY VOLTAGE (V) 8
3830 G03
2 0 -2 -4 -6 -8
-10
500 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3830 G05
Error Amplifier Sink/Source Current vs Temperature
40
200
Error Amplifier Open-Loop Gain vs Temperature
60
55
50
45
-40 125
40 -50 -25
75 0 25 50 TEMPERATURE (C)
100
125
3830 G06
2830 G07
Oscillator Frequency vs FREQSET Input Current
1.5
Oscillator (VSAWH - VSAWL) vs External Sync Frequency
TA = 25C
1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 TA = 25C
10 -20 -10 0 -30 FREQSET INPUT CURRENT (A)
20
3830 G09
0.5 100
300 200 400 EXTERNAL SYNC FREQUENCY (kHz)
500
3830 G10
sn3830 3830fs
LTC3830/LTC3830-1 TYPICAL PERFOR A CE CHARACTERISTICS
Maximum G1 Duty Cycle vs Temperature
100 99
MAXIMUM G1 DUTY CYCLE (%)
VFB = 0V REFER TO FIGURE 3
IMAX SINK CURRENT (A)
98 97 96 95 94 93 92 91 -50 -25 0 25 75 50 TEMPERATURE (C) 100 125
14 12 10 8 6 4 - 50 - 25 0 75 50 25 TEMPERATURE (C) 100 125
OUTPUT VOLTAGE (V)
Output Current Limit Threshold vs Temperature
15
SOFT-START SOURCE CURRENT (A)
14
OUTPUT CURRENT LIMIT (A)
13 12 11 10 9 8 7 6
-10 -11 -12 -13 -14 -15 -16 - 50 - 25 0 75 50 25 TEMPERATURE (C) 100 125
SOFT-START SINK CURRENT (mA)
REFER TO FIGURE 12 AND NOTE 10 OF THE ELECTRICAL CHARACTERISTICS RIMAX = 20k
5 -50 -25
50 25 0 75 TEMPERATURE (C)
UNDERVOLTAGE LOCKOUT THRESHOLD VOLTAGE (V)
Undervoltage Lockout Threshold Voltage vs Temperature
3.0 1.6
VCC OPERATING SUPPLY CURRENT (mA)
2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125
PVCC SUPPLY CURRENT (mA)
UW
3830 G11
IMAX Sink Current vs Temperature
20 18 16 3.5
Output Overcurrent Protection
3.0 TA = 25C REFER TO FIGURE 12 RIMAX = 20k 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 OUTPUT CURRENT (A) 12 14
3830 G12
3830 G13
Soft-Start Source Current vs Temperature
-8 -9 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25
Soft-Start Sink Current vs (VIFB - VIMAX)
TA = 25C
100
125
0 -150
-125
-100
-50 -75 VIFB - VIMAX (mV)
-25
0
3830 G16
3830 G14
3830 G15
VCC Operating Supply Current vs Temperature
1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 FREQSET FLOATING 90 80 70 60 50 40 30 20 10 0
PVCC Supply Current vs Oscillator Frequency
TA = 25C G1 AND G2 LOADED WITH 6800pF, PVCC1,2 = 12V G1 AND G2 LOADED WITH 1000pF, PVCC1,2 = 5V G1 AND G2 LOADED WITH 6800pF, PVCC1,2 = 5V
0
400 100 300 200 OSCILLATOR FREQUENCY (kHz)
500
3830 G19
3830 G17
3830 G18
sn3830 3830fs
5
LTC3830/LTC3830-1 TYPICAL PERFOR A CE CHARACTERISTICS
PVCC Supply Current vs Gate Capacitance
50 TA = 25C 200 180 160 PVCC1,2 = 12V 30
G1 RISE/FALL TIME (ns)
PVCC SUPPLY CURRENT (mA)
40
20 PVCC1,2 = 5V 10
0
0
1 2 3 4 5 6 7 8 9 10 GATE CAPACITANCE AT G1 AND G2 (nF)
3830 G20
PI FU CTIO S
(16-Lead LTC3830/8-Lead LTC3830/LTC3830-1)
G1 (Pin 1/Pin 1/Pin 1): Top Gate Driver Output. Connect this pin to the gate of the upper N-channel MOSFET, Q1. This output swings from PGND to PVCC1. It remains low if G2 is high or during shutdown mode. PVCC1 (Pin 2/Pin 2/Pin 2): Power Supply Input for G1. Connect this pin to a potential of at least VIN + VGS(ON)(Q1). This potential can be generated using an external supply or charge pump. PGND (Pin 3/Pin 3/Pin 3): Power Ground. Both drivers return to this pin. Connect this pin to a low impedance ground in close proximity to the source of Q2. Refer to the Layout Consideration section for more details on PCB layout techniques. The LTC3830-1 and the 8-lead LTC3830 have PGND and GND tied together internally at Pin 3. GND (Pin 4/Pin 3/Pin 3): Signal Ground. All low power internal circuitry returns to this pin. To minimize regulation errors due to ground currents, connect GND to PGND right at the LTC3830. SENSE-, FB, SENSE+ (Pins 5, 6, 7/Pin 4/Pin 4): These three pins connect to the internal resistor divider and input of the error amplifier. To use the internal divider to set the output voltage to 3.3V, connect SENSE+ to the positive terminal of the output capacitor and SENSE- to the negative terminal. FB should be left floating. To use an external
6
UW
G1 Rise/Fall Time vs Gate Capacitance
TA = 25C
VOUT 50mV/DIV
Transient Response
140 120 100 80 60 40 20 0 0 tf AT PVCC1,2 = 12V tr AT PVCC1,2 = 12V 1 2 3 4 5 6 7 8 9 10 GATE CAPACITANCE AT G1 AND G2 (nF)
3830 G21
tf AT PVCC1,2 = 5V tr AT PVCC1,2 = 5V
ILOAD 2AV/DIV
50s/DIV
3830 G22.tif
U
U
U
resistor divider to set the output voltage, float SENSE+ and SENSE- and connect the external resistor divider to FB. The internal resistor divider is not included in the LTC3830-1 and the 8-lead LTC3830. SHDN (Pin 8/Pin 5/NA): Shutdown. A TTL compatible low level at SHDN for longer than 100s puts the LTC3830 into shutdown mode. In shutdown, G1 and G2 go low, all internal circuits are disabled and the quiescent current drops to 10A max. A TTL compatible high level at SHDN allows the part to operate normally. This pin also doubles as an external clock input to synchronize the internal oscillator with an external clock. The shutdown function is disabled in the LTC3830-1. SS (Pin 9/NA/Pin 5): Soft-Start. Connect this pin to an external capacitor, CSS, to implement a soft-start function. If the LTC3830 goes into current limit, CSS is discharged to reduce the duty cycle. CSS must be selected such that during power-up, the current through Q1 will not exceed the current limit level. The soft-start function is disabled in the 8-lead LTC3830. COMP (Pin 10/Pin 6/Pin 6): External Compensation. This pin internally connects to the output of the error amplifier and input of the PWM comparator. Use a RC + C network at this pin to compensate the feedback loop to provide optimum transient response.
sn3830 3830fs
LTC3830/LTC3830-1
PI FU CTIO S
FREQSET (Pin 11/NA/NA): Frequency Set. Use this pin to adjust the free-running frequency of the internal oscillator. With the pin floating, the oscillator runs at about 200kHz. A resistor from FREQSET to ground speeds up the oscillator; a resistor to VCC slows it down. IMAX (Pin 12/NA/NA): Current Limit Threshold Set. IMAX sets the threshold for the internal current limit comparator. If IFB drops below IMAX with G1 on, the LTC3830 goes into current limit. IMAX has an internal 12A pull-down to GND. Connect this pin to the main VIN supply at the drain of Q1, through an external resistor to set the current limit threshold. Connect a 0.1F decoupling capacitor across this resistor to filter switching noise. IFB (Pin 13/NA/NA): Current Limit Sense. Connect this pin to the switching node at the source of Q1 and the drain of Q2 through a 1k resistor. The 1k resistor is required to prevent voltage transients from damaging IFB.This pin is used for sensing the voltage drop across the upper N-channel MOSFET, Q1. VCC (Pin 14/Pin 7/Pin 7): Power Supply Input. All low power internal circuits draw their supply from this pin. Connect this pin to a clean power supply, separate from the main VIN supply at the drain of Q1. This pin requires a 4.7F bypass capacitor. The LTC3830-1 and the 8-lead LTC3830 have VCC and PVCC2 tied together at Pin 7 and require a 10F bypass capacitor to GND. PVCC2 (Pin 15/Pin 7/Pin 7): Power Supply Input for G2. Connect this pin to the main high power supply. G2 (Pin 16/Pin 8/Pin 8): Bottom Gate Driver Output. Connect this pin to the gate of the lower N-channel MOSFET, Q2. This output swings from PGND to PVCC2. It remains low when G1 is high or during shutdown mode. To prevent output undershoot during a soft-start cycle, G2 is held low until G1 first goes high. (FFBG in Block Diagram.)
BLOCK DIAGRA
SHDN
FREQSET
COMP
12A SS QSS POR
ERR
+
-
VREF CC
+
-
W
U
U
U
100s DELAY INTERNAL OSCILLATOR
LOGIC AND THERMAL SHUTDOWN POWER DOWN
DISABLE GATE DRIVE
VCC
PVCC1 S PWM R Q PVCC2 Q G1
FFBG S R Q ENABLE G2
G2 PGND GND
MIN
MAX
-
+
-
+
FB 18k 11.2k
VREF - 3%
VREF + 3% IFB VREF VREF - 3% VREF + 3%
SENSE + SENSE -
- +
12A
IMAX
BG
3830 BD
sn3830 3830fs
7
LTC3830/LTC3830-1
TEST CIRCUITS
5V
PVCC VSHDN VCC SHDN NC NC NC NC FB SS FREQSET COMP IMAX GND VCC PVCC2 PVCC1 IFB G1 6800pF LTC3830 G2 PGND SENSE - SENSE +
3830 F02
+
10F IFB VCOMP COMP LTC3830 VFB FB IMAX GND PGND G2 6800pF
3830 F03
0.1F
VCC
PVCC1 PVCC2 G1 6800pF G1 RISE/FALL
G2 RISE/FALL
6800pF
Figure 2
Figure 3
APPLICATIO S I FOR ATIO
OVERVIEW
The LTC3830 is a voltage mode feedback, synchronous switching regulator controller (see Block Diagram) designed for use in high power, low voltage step-down (buck) converters. It includes an onboard PWM generator, a precision reference trimmed to 0.8%, two high power MOSFET gate drivers and all necessary feedback and control circuitry to form a complete switching regulator circuit. The PWM loop nominally runs at 200kHz. The 16-lead versions of the LTC3830 include a current limit sensing circuit that uses the topside external N-channel power MOSFET as a current sensing element, eliminating the need for an external sense resistor. Also included in the 16-lead version and the LTC3830-1 is an internal soft-start feature that requires only a single external capacitor to operate. In addition, 16-lead parts feature an adjustable oscillator that can free run or synchronize to external signal with frequencies from 100kHz to 500kHz, allowing added flexibility in external component selection. The 8-lead version does not include current limit, internal soft-start and frequency adjustability. The LTC3830-1 does not include current limit, frequency adjustability, external synchronization and the shutdown function.
8
U
THEORY OF OPERATION Primary Feedback Loop The LTC3830/LTC3830-1 sense the output voltage of the circuit at the output capacitor and feeds this voltage back to the internal transconductance error amplifier, ERR, through a resistor divider network. The error amplifier compares the resistor-divided output voltage to the internal 1.265V reference and outputs an error signal to the PWM comparator. This error signal is compared with a fixed frequency ramp waveform, from the internal oscillator, to generate a pulse width modulated signal. This PWM signal drives the external MOSFETs through the G1 and G2 pins. The resulting chopped waveform is filtered by LO and COUT which closes the loop. Loop compensation is achieved with an external compensation network at the COMP pin, the output node of the error amplifier. MIN, MAX Feedback Loops Two additional comparators in the feedback loop provide high speed output voltage correction in situations where the error amplifier may not respond quickly enough. MIN compares the feedback signal to a voltage 40mV below the internal reference. If the signal is below the comparator threshold, the MIN comparator overrides the error amplifier and forces the loop to maximum duty cycle, >91%.
sn3830 3830fs
W
UU
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
Similarly, the MAX comparator forces the output to 0% duty cycle if the feedback signal is greater than 40mV above the internal reference. To prevent these two comparators from triggering due to noise, the MIN and MAX comparators' response times are deliberately delayed by two to three microseconds. These two comparators help prevent extreme output perturbations with fast output load current transients, while allowing the main feedback loop to be optimally compensated for stability. Thermal Shutdown The LTC3830/LTC3830-1 have a thermal protection circuit that disables both gate drivers if activated. If the chip junction temperature reaches 150C, both G1 and G2 are pulled low. G1 and G2 remain low until the junction temperature drops below 125C, after which, the chip resumes normal operation. Soft-Start and Current Limit The 16-lead LTC3830 devices include a soft-start circuit that is used for start-up and current limit operation. The LTC3830-1 only has the soft-start function; the current limit function is disabled. The 8-lead LTC3830 has both the soft-start and current limit function disabled. The SS pin requires an external capacitor, CSS, to GND with the value determined by the required soft-start time. An internal 12A current source is included to charge CSS. During power-up, the COMP pin is clamped to a diode drop (B-E junction of QSS in the Block Diagram) above the voltage at the SS pin. This prevents the error amplifier from forcing the loop to maximum duty cycle. The LTC3830/LTC3830-1 operate at low duty cycle as the SS pin rises above 0.6V (VCOMP 1.2V). As SS continues to rise, QSS turns off and the error amplifier takes over to regulate the output. The MIN comparator is disabled during soft-start to prevent it from overriding the soft-start function. The 16-lead LTC3830 devices include yet another feedback loop to control operation in current limit. Just before every falling edge of G1, the current comparator, CC, samples and holds the voltage drop measured across the external upper MOSFET, Q1, at the IFB pin. CC compares
U
the voltage at IFB to the voltage at the IMAX pin. As the peak current rises, the measured voltage across Q1 increases due to the drop across the RDS(ON) of Q1. When the voltage at IFB drops below IMAX, indicating that Q1's drain current has exceeded the maximum level, CC starts to pull current out of CSS, cutting the duty cycle and controlling the output current level. The CC comparator pulls current out of the SS pin in proportion to the voltage difference between IFB and IMAX. Under minor overload conditions, the SS pin falls gradually, creating a time delay before current limit takes effect. Very short, mild overloads may not affect the output voltage at all. More significant overload conditions allow the SS pin to reach a steady state, and the output remains at a reduced voltage until the overload is removed. Serious overloads generate a large overdrive at CC, allowing it to pull SS down quickly and preventing damage to the output components. By using the RDS(ON) of Q1 to measure the output current, the current limiting circuit eliminates an expensive discrete sense resistor that would otherwise be required. This helps minimize the number of components in the high current path. The current limit threshold can be set by connecting an external resistor RIMAX from the IMAX pin to the main VIN supply at the drain of Q1. The value of RIMAX is determined by: RIMAX = (ILMAX)(RDS(ON)Q1)/IIMAX where: ILMAX = ILOAD + (IRIPPLE/2) ILOAD = Maximum load current IRIPPLE = Inductor ripple current =
W
UU
( VIN - VOUT )( VOUT ) (fOSC )(LO )(VIN)
fOSC = LTC3830 oscillator frequency = 200kHz LO = Inductor value RDS(ON)Q1 = On-resistance of Q1 at ILMAX IIMAX = Internal 12A sink current at IMAX
sn3830 3830fs
9
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
The RDS(ON) of Q1 usually increases with temperature. To keep the current limit threshold constant, the internal 12A sink current at IMAX is designed with a positive temperature coefficient to provide first order correction for the temperature coefficient of RDS(ON)Q1. In order for the current limit circuit to operate properly and to obtain a reasonably accurate current limit threshold, the IIMAX and IFB pins must be Kelvin sensed at Q1's drain and source pins. In addition, connect a 0.1F decoupling capacitor across RIMAX to filter switching noise. Otherwise, noise spikes or ringing at Q1's source can cause the actual current limit to be greater than the desired current limit set point. Due to switching noise and variation of RDS(ON), the actual current limit trip point is not highly accurate. The current limiting circuitry is primarily meant to prevent damage to the power supply circuitry during fault conditions. The exact current level where the limiting circuit begins to take effect will vary from unit to unit as the RDS(ON) of Q1 varies. Typically, RDS(ON) varies as much as 40% and with 25% variation on the LTC3830's IMAX current, this can give a 65% variation on the current limit threshold. The RDS(ON) is high if the VGS applied to the MOSFET is low. This occurs during power up, when PVCC1 is ramping up. To prevent the high RDS(ON) from activating the current limit, the LTC3830 disables the current limit circuit if PVCC1 is less than 2.5V above VCC. To ensure proper operation of the current limit circuit, PVCC1 must be at least 2.5V above VCC when G1 is high. PVCC1 can go low when G1 is low, allowing the use of an external charge pump to power PVCC1.
VIN LTC3830
RIMAX
0.1F
+
CC 12A
12 IMAX IFB G1 1k G2 Q2 Q1 LO
-
13
Figure 4. Current Limit Setting
10
U
Oscillator Frequency The LTC3830 includes an onboard current controlled oscillator that typically free-runs at 200kHz. The oscillator frequency can be adjusted by forcing current into or out of the FREQSET pin. With the pin floating, the oscillator runs at about 200kHz. Every additional 1A of current into/out of the FREQSET pin decreases/increases the frequency by 10kHz. The pin is internally servoed to 1.265V, connecting a 50k resistor from FREQSET to ground forces 25A out of the pin, causing the internal oscillator to run at approximately 450kHz. Forcing an external 10A current into FREQSET cuts the internal frequency to 100kHz. An internal clamp prevents the oscillator from running slower than about 50kHz. Tying FREQSET to VCC forces the chip to run at this minimum speed. The LTC3830-1 and the 8-lead LTC3830 do not have this frequency adjustment function. Shutdown The LTC3830 includes a low power shutdown mode, controlled by the logic at the SHDN pin. A high at SHDN allows the part to operate normally. A low level at SHDN for more than 100s forces the LTC3830 into shutdown mode. In this mode, all internal switching stops, the COMP and SS pins pull to ground and Q1 and Q2 turn off. The LTC3830 supply current drops to <10A, although offstate leakage in the external MOSFETs may cause the total VIN current to be some what higher, especially at elevated temperatures. If SHDN returns high, the LTC3830 reruns a soft-start cycle and resumes normal operation. The LTC3830-1 does not have this shutdown function. External Clock Synchronization The LTC3830 SHDN pin doubles as an external clock input for applications that require a synchronized clock. An internal circuit forces the LTC3830 into external synchronization mode if a negative transition at the SHDN pin is detected. In this mode, every negative transition on the SHDN pin resets the internal oscillator and pulls the ramp signal low, this forces the LTC3830 internal oscillator to lock to the external clock frequency. The LTC3830-1 does not have this external synchronization function.
+
CIN
W
UU
+
VOUT COUT
3830 F04
sn3830 3830fs
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
The LTC3830 internal oscillator can be externally synchronized from 100kHz to 500kHz. Frequencies above 300kHz can cause a decrease in the maximum obtainable duty cycle as rise/fall time and propagation delay take up a larger percentage of the switch cycle. Circuits using these frequencies should be checked carefully in applications where operation near dropout is important--like 3.3V to 2.5V converters. The low period of this clock signal must not be >100s, or else the LTC3830 enters shutdown mode. Figure 5 describes the operation of the external synchronization function. A negative transition at the SHDN pin forces the internal ramp signal low to restart a new PWM cycle. Notice that with the traditional sync method, the ramp amplitude is lowered as the external clock frequency goes higher. The effect of this decrease in ramp amplitude increases the open-loop gain of the controller feedback loop. As a result, the loop crossover frequency increases and it may cause the feedback loop to be unstable if the phase margin is insufficient.
SHDN
TRADITIONAL SYNC METHOD WITH EARLY RAMP TERMINATION
200kHz FREE RUNNING RAMP SIGNAL
RAMP SIGNAL WITH EXT SYNC
RAMP AMPLITUDE ADJUSTED LTC3830 KEEPS RAMP AMPLITUDE CONSTANT UNDER SYNC
INTERNAL CIRCUITRY
Figure 5. External Synchronization Operation
U
To overcome this problem, the LTC3830 monitors the peak voltage of the ramp signal and adjusts the oscillator charging current to maintain a constant ramp peak. Input Supply Considerations/Charge Pump The 16-lead LTC3830 requires four supply voltages to operate: VIN for the main power input, PVCC1 and PVCC2 for MOSFET gate drive and a clean, low ripple VCC for the LTC3830 internal circuitry (Figure 6). The LTC3830-1 and the 8-lead LTC3830 have the PVCC2 and VCC pins tied together inside the package (Figure 7). This pin, brought out as VCC/PVCC2 , has the same low ripple requirements as the 16-lead part, but must also be able to supply the gate drive current to Q2. In many applications, VCC can be powered from VIN through an RC filter. This supply can be as low as 3V. The low quiescent current (typically 800A) allows the use of relatively large filter resistors and correspondingly small
VCC PVCC2 PVCC1 VIN G1 Q1 LO VOUT G2 INTERNAL CIRCUITRY Q2
W
UU
+
COUT
3830 F6
LTC3830 (16-LEAD)
Figure 6. 16-Lead Power Supplies
VCC/PVCC2 PVCC1 VIN
G1
Q1 LO VOUT
G2
+
Q2 COUT
3830 F7
LTC3830 (8-LEAD)
3830 F05
Figure 7. 8-Lead Power Supplies
sn3830 3830fs
11
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
filter capacitors. 100 and 4.7F usually provide adequate filtering for VCC. For best performance, connect the 4.7F bypass capacitor as close to the LTC3830 VCC pin as possible. Gate drive for the top N-channel MOSFET Q1 is supplied from PVCC1. This supply must be above VIN (the main power supply input) by at least one power MOSFET VGS(ON) for efficient operation. An internal level shifter allows PVCC1 to operate at voltages above VCC and VIN, up to 14V maximum. This higher voltage can be supplied with a separate supply, or it can be generated using a charge pump. Gate drive for the bottom MOSFET Q2 is provided through PVCC2 for the 16-lead LTC3830 or VCC/PVCC2 for the LTC3830-1 and the 8-lead LTC3830. This supply only needs to be above the power MOSFET VGS(ON) for efficient operation. PVCC2 can also be driven from the same supply/ charge pump for the PVCC1, or it can be connected to a lower supply to improve efficiency. Figure 8 shows a tripling charge pump circuit that can be used to provide 2VIN and 3VIN gate drive for the external top and bottom MOSFETs respectively. These should fully enhance MOSFETs with 5V logic level thresholds. This circuit provides 3VIN - 3VF to PVCC1 while Q1 is ON and 2VIN - 2VF to PVCC2 where VF is the forward voltage of the Schottky diodes. The circuit requires the use of Schottky diodes to minimize forward drop across the diodes at start-up. The tripling charge pump circuit can rectify any
DZ 12V 1N5242 1N5817 1N5817 0.1F 0.1F Q1 LO VOUT G2 VIN 1N5817
10F
PVCC2
PVCC1 G1
Q2
LTC3830
Figure 8. Tripling Charge Pump
12
U
ringing at the drain of Q2 and provide more than 3VIN at PVCC1; a 12V zener diode should be included from PVCC1 to PGND to prevent transients from damaging the circuitry at PVCC1 or the gate of Q1. Care should be taken when using a charge pump to power PVCC1 in applications with low VCC supply voltages (less than 4V) or high switching frequencies. The charge pump capacitors refresh when the G2 pin goes high and the switch node is pulled low by Q2. The G2 on-time becomes narrow when LTC3830 operates at maximum duty cycle (95% typical), which can occur if the input supply rises more slowly than the soft-start capacitor or the input voltage droops during load transients. If the G2 on-time gets so narrow that the switch node fails to pull completely to ground, the charge pump voltage may collapse or fail to start, causing excessive dissipation in external MOSFET Q1. This is most likely with low VCC voltages and high switching frequencies, coupled with large external MOSFETs which slow the G2 and switch node slew rates. Workarounds include: * Increasing the soft-start capacitor to limit the duty cycle at start up * Using smaller MOSFETs with lower gate capacitance (where possible) to reduce the G2 rise/fall time and switch node slew rates * Using an external higher voltage supply to power PVCC1 if available Another alternative is to add an external circuit to limit the duty cycle when PVCC1 is low, as shown in Figure 9b. If the charge pump is not running, PVCC1 will be less than or equal to VCC and the voltage at the soft-start pin will be about (VCC/6 + VBE). This is about 1.2V with a VCC of 3.3V, which limits the duty cycle to about 50% and allows the charge pump to start up. Once PVCC1 rises higher than (VCC + VTQ3), the voltage at the soft-start pin goes high and the limit on duty cycle is removed. For applications with a 5V or higher VIN supply, PVCC2 can be tied to VIN if a logic level MOSFET is used. PVCC1 can be supplied using a doubling charge pump as shown in Figure 9a. This circuit provides 2VIN - VF to PVCC1 while Q1 is ON.
sn3830 3830fs
W
UU
+
COUT
3830 F08
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
VIN OPTIONAL USE FOR VIN 7V DZ 12V 1N5242 PVCC2 PVCC1 G1 MBR0530T1
0.1F Q1 LO VOUT
G2
Q2
LTC3830
Figure 9a. Doubling Charge Pump
Figure 12 shows a typical 5V to 3.3V application using a doubling charge pump to generate PVCC1. Power MOSFETs Two N-channel power MOSFETs are required for most LTC3830 circuits. These should be selected based primarily on threshold voltage and on-resistance considerations. Thermal dissipation is often a secondary concern in high efficiency designs. The required MOSFET threshold should be determined based on the available power supply voltages and/or the complexity of the gate drive charge pump scheme. In 3.3V input designs where an auxiliary 12V supply is available to power PVCC1 and PVCC2, standard MOSFETs with RDS(ON) specified at VGS = 5V or 6V can be used with good results. The current drawn from this supply varies with the MOSFETs used and the LTC3830's operating frequency, but is generally less than 50mA. LTC3830 applications that use 5V or lower VIN voltage and a doubling/tripling charge pump to generate PVCC1 and PVCC2, do not provide enough gate drive voltage to fully enhance standard power MOSFETs. Under this condition, the effective MOSFET RDS(ON) may be quite high, raising the dissipation in the FETs and reducing efficiency. Logic level FETs are the recommended choice for 5V or lower
U
VIN D2 D1 10F PVCC2 PVCC1 G1 Q3 BSS284 SS Q4 3906 G2 0.1F Q1 LO VOUT
W
UU
+
COUT
3830 F09a
R1 1M R2 200k
+
Q2 COUT
3830 F09b
LTC3830
Figure 9b. Duty Cycle Clamp Circuit
voltage systems. Logic level FETs can be fully enhanced with a doubler/tripling charge pump and will operate at maximum efficiency. After the MOSFET threshold voltage is selected, choose the RDS(ON) based on the input voltage, the output voltage, allowable power dissipation and maximum output current. In a typical LTC3830 circuit, operating in continuous mode, the average inductor current is equal to the output load current. This current flows through either Q1 or Q2 with the power dissipation split up according to the duty cycle:
VOUT VIN V V -V DC(Q2) = 1 - OUT = IN OUT VIN VIN DC(Q1) =
The RDS(ON) required for a given conduction loss can now be calculated by rearranging the relation P = I2R.
RDS(ON)Q1 = RDS(ON)Q2 = PMAX(Q1) DC(Q1) * (ILOAD )2 PMAX(Q2 ) DC(Q2) * (ILOAD)2 = = VIN * PMAX(Q1) VOUT * (ILOAD )2 VIN * PMAX(Q2 ) ( VIN - VOUT ) * (ILOAD)2
sn3830 3830fs
13
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
PMAX should be calculated based primarily on required efficiency or allowable thermal dissipation. A typical high efficiency circuit designed for 5V input and 3.3V at 10A output might allow no more than 3% efficiency loss at full load for each MOSFET. Assuming roughly 90% efficiency at this current level, this gives a PMAX value of: (3.3V)(10A/0.9)(0.03) = 1.1W per FET and a required RDS(ON) of:
(5V) * (1.1W) RDS(ON)Q1 = = 0.017 (3.3V)(10 A)2 (5V) * (1.1W) RDS(ON)Q2 = = 0.032 (5V - 3.3V)(10 A)2
Note that the required RDS(ON) for Q2 is roughly twice that of Q1 in this example. This application might specify a single 0.03 device for Q2 and parallel two more of the same devices to form Q1. Note also that while the required RDS(ON) values suggest large MOSFETs, the power dissipation numbers are only 1.1W per device or less; large TO-220 packages and heat sinks are not necessarily required in high efficiency applications. Siliconix Si4410DY
Table 1. Recommended MOSFETs for LTC3830 Applications
RDS(ON) AT 25C (m) 19 20 35 8 10 9 19 28 37
PARTS Siliconix SUD50N03-10 TO-252 Siliconix Si4410DY SO-8 ON Semiconductor MTD20N03HDL DPAK Fairchild FDS6670A S0-8 Fairchild FDS6680 SO-8 ON Semiconductor MTB75N03HDL DD PAK IR IRL3103S DD PAK IR IRLZ44 TO-220 Fuji 2SK1388 TO-220
Note: Please refer to the manufacturer's data sheet for testing conditions and detailed information.
sn3830 3830fs
14
U
or International Rectifier IRF7413 (both in SO-8) or Siliconix SUD50N03-10 (TO-252) or ON Semiconductor MTD20N03HDL (DPAK) are small footprint surface mount devices with RDS(ON) values below 0.03 at 5V of VGS that work well in LTC3830 circuits. Using a higher PMAX value in the RDS(ON) calculations generally decreases the MOSFET cost and the circuit efficiency and increases the MOSFET heat sink requirements. Table 1 highlights a variety of power MOSFETs for use in LTC3830 applications. Inductor Selection The inductor is often the largest component in an LTC3830 design and must be chosen carefully. Choose the inductor value and type based on output slew rate requirements. The maximum rate of rise of inductor current is set by the inductor's value, the input-to-output voltage differential and the LTC3830's maximum duty cycle. In a typical 5V input, 3.3V output application, the maximum rise time will be:
W
UU
DCMAX * ( VIN - VOUT ) 1.615 A = LO LO s
RATED CURRENT (A) 15 at 25C 10 at 100C 10 at 25C 8 at 70C 20 at 25C 16 at 100C 13 at 25C 11.5 at 25C 75 at 25C 59 at 100C 64 at 25C 45 at 100C 50 at 25C 36 at 100C 35 at 25C
TYPICAL INPUT CAPACITANCE CISS (pF) 3200 2700 880 3200 2070 4025 1600 3300 1750
JC (C/W) 1.8
TJMAX (C) 175 150
1.67 25 25 1 1.4 1 2.08
150 150 150 150 175 175 150
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
where LO is the inductor value in H. With proper frequency compensation, the combination of the inductor and output capacitor values determine the transient recovery time. In general, a smaller value inductor improves transient response at the expense of ripple and inductor core saturation rating. A 2H inductor has a 0.81A/s rise time in this application, resulting in a 6.2s delay in responding to a 5A load current step. During this 6.2s, the difference between the inductor current and the output current is made up by the output capacitor. This action causes a temporary voltage droop at the output. To minimize this effect, the inductor value should usually be in the 1H to 5H range for most 5V input LTC3830 circuits. To optimize performance, different combinations of input and output voltages and expected loads may require different inductor values. Once the required value is known, the inductor core type can be chosen based on peak current and efficiency requirements. Peak current in the inductor will be equal to the maximum output load current plus half of the peak-topeak inductor ripple current. Ripple current is set by the inductor value, the input and output voltage and the operating frequency. The ripple current is approximately equal to:
IRIPPLE =
( VIN - VOUT ) * ( VOUT ) fOSC * LO * VIN
fOSC = LTC3830 oscillator frequency = 200kHz LO = Inductor value Solving this equation with our typical 5V to 3.3V application with a 2H inductor, we get:
(5V - 3.3V) * 3.3V = 2.8 AP-P 200kHz * 2H * 5V
U
Peak inductor current at 10A load: 10A + (2.8A/2) = 11.4A The ripple current should generally be between 10% and 40% of the output current. The inductor must be able to withstand this peak current without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. Note that in circuits not employing the current limit function, the current in the inductor may rise above this maximum under short-circuit or fault conditions; the inductor should be sized accordingly to withstand this additional current. Inductors with gradual saturation characteristics are often the best choice. Input and Output Capacitors A typical LTC3830 design places significant demands on both the input and the output capacitors. During normal steady load operation, a buck converter like the LTC3830 draws square waves of current from the input supply at the switching frequency. The peak current value is equal to the output load current plus 1/2 the peak-to-peak ripple current. Most of this current is supplied by the input bypass capacitor. The resulting RMS current flow in the input capacitor heats it and causes premature capacitor failure in extreme cases. Maximum RMS current occurs with 50% PWM duty cycle, giving an RMS current value equal to IOUT/2. A low ESR input capacitor with an adequate ripple current rating must be used to ensure reliable operation. Note that capacitor manufacturers' ripple current ratings are often based on only 2000 hours (3 months) lifetime at rated temperature. Further derating of the input capacitor ripple current beyond the manufacturer's specification is recommended to extend the useful life of the circuit. Lower operating temperature has the largest effect on capacitor longevity.
sn3830 3830fs
W
UU
15
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
The output capacitor in a buck converter under steadystate conditions sees much less ripple current than the input capacitor. Peak-to-peak current is equal to inductor ripple current, usually 10% to 40% of the total load current. Output capacitor duty places a premium not on power dissipation but on ESR. During an output load transient, the output capacitor must supply all of the additional load current demanded by the load until the LTC3830 adjusts the inductor current to the new value. ESR in the output capacitor results in a step in the output voltage equal to the ESR value multiplied by the change in load current. An 5A load step with a 0.05 ESR output capacitor results in a 250mV output voltage shift; this is 7.6% of the output voltage for a 3.3V supply! Because of the strong relationship between output capacitor ESR and output load transient response, choose the output capacitor for ESR, not for capacitance value. A capacitor with suitable ESR will usually have a larger capacitance value than is needed to control steady-state output ripple. Electrolytic capacitors rated for use in switching power supplies with specified ripple current ratings and ESR can be used effectively in LTC3830 applications. OS-CON electrolytic capacitors from Sanyo and other manufacturers give excellent performance and have a very high performance/size ratio for electrolytic capacitors. Surface mount applications can use either electrolytic or dry tantalum capacitors. Tantalum capacitors must be surge tested and specified for use in switching power supplies. Low cost, generic tantalums are known to have very short lives followed by explosive deaths in switching power supply applications. Other capacitors that can be used include the Sanyo POSCAP and MV-WX series. A common way to lower ESR and raise ripple current capability is to parallel several capacitors. A typical LTC3830 application might exhibit 5A input ripple current. Sanyo OS-CON capacitors, part number 10SA220M (220F/10V), feature 2.3A allowable ripple current at 85C; three in parallel at the input (to withstand the input ripple current) meet the above requirements. Similarly, Sanyo POSCAP 4TPB470M (470F/4V) capacitors have
COMP
10
RC CC C1
ERR
Figure 10a. Compensation Pin Hook-Up
16
-
+
U
a maximum rated ESR of 0.04; three in parallel lower the net output capacitor ESR to 0.013. Feedback Loop Compensation The LTC3830 voltage feedback loop is compensated at the COMP pin, which is the output node of the error amplifier. The feedback loop is generally compensated with an RC + C network from COMP to GND as shown in Figure 10a. Loop stability is affected by the values of the inductor, the output capacitor, the output capacitor ESR, the error amplifier transconductance and the error amplifier compensation network. The inductor and the output capacitor create a double pole at the frequency:
fLC = 1/ 2 (LO )(COUT )
W
UU
[
]
The ESR of the output capacitor and the output capacitor value form a zero at the frequency: fESR = 1/ [2 (ESR)(COUT )] The compensation network used with the error amplifier must provide enough phase margin at the 0dB crossover frequency for the overall open-loop transfer function. The zero and pole from the compensation network are: fZ = 1/[2(RC)(CC)] and fP = 1/[2(RC)(C1)] respectively
7 SENSE +
LTC3830 C2 R2 VFB
6
R1 SENSE -
5
VREF
3830 F10a
sn3830 3830fs
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
Figure 10b shows the Bode plot of the overall transfer function. When low ESR output capacitors (Sanyo OS-CON) are used, the ESR zero can be high enough in frequency that it provides little phase boost at the loop crossover frequency. As a result, the phase margin becomes inadequate and the load transient is not optimized. To resolve this problem, a small capacitor can be connected between the top of the resistor divider network and the VFB pin to create a pole-zero pair in the loop compensation. The zero location is prior to the pole location and thus, phase lead can be added to boost the phase margin at the loop crossover frequency. The pole and zero locations are located at: fZC2 = 1/[2(R2)(C2)] and fPC2 = 1/[2(R1||R2)(C2)] where R1||R2 is the parallel combination resistance of R1 and R2. Choose C2 so that the zero is located at a lower frequency compared to fCO and the pole location is high enough that the closed loop has enough phase margin for stability. Figure 10c shows the Bode plot using phase lead compensation around the LTC3830 resistor divider network. Note: This technique is effective only when R1 >> R2 i.e., at high output voltages only so that the pole and zero are sufficiently separated.
fZ
LOOP GAIN
fSW = LTC3830 SWITCHING FREQUENCY fCO = CLOSED-LOOP CROSSOVER FREQUENCY
LOOP GAIN
20dB/DECADE 20dB/DECADE fCO fP fLC fESR fCO FREQUENCY fLC fZC2 fESR
3830 F10b
Figure 10b. Bode Plot of the LTC3830 Overall Transfer Function
U
Although a mathematical approach to frequency compensation can be used, the added complication of input and/or output filters, unknown capacitor ESR, and gross operating point changes with input voltage, load current variations, all suggest a more practical empirical method. This can be done by injecting a transient current at the load and using an RC network box to iterate toward the final values, or by obtaining the optimum loop response using a network analyzer to find the actual loop poles and zeros. Table 2 shows the suggested compensation component value for 5V to 3.3V applications based on Sanyo OS-CON 4SP820M low ESR output capacitors.
Table 2. Recommended Compensation Network for 5V to 3.3V Applications Using Multiple Paralleled 820F Sanyo OS-CON 4SP820M Output Capacitors
L1 (H) 1.2 1.2 1.2 2.4 2.4 2.4 4.7 4.7 4.7 COUT (F) 1640 2460 4100 1640 2460 4100 1640 2460 4100 RC (k) 6.2 12 12 15 20 36 30 36 82 CC (nF) 3.3 3.3 1.8 2.7 1.0 1.0 1.8 1.0 1.0 C1 (pF) 470 470 220 330 220 220 330 180 180 C2 (pF) 1000 1000 1000 1000 1000 1000 1000 1000 1000
fSW = LTC3830 SWITCHING FREQUENCY fCO = CLOSED-LOOP CROSSOVER FREQUENCY fZ fP fPC2 FREQUENCY
3830 F10c
W
UU
Figure 10c. Bode Plot of the LTC3830 Overall Transfer Function Using a Low ESR Output Capacitor
sn3830 3830fs
17
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
Table 3 shows the suggested compensation component values for 5V to 3.3V applications based on 470F Sanyo POSCAP 4TPB470M output capacitors.
Table 3. Recommended Compensation Network for 5V to 3.3V Applications Using Multiple Paralleled 470F Sanyo POSCAP 4TPB470M Output Capacitors
L1 (H) 1.2 1.2 1.2 2.4 2.4 2.4 4.7 4.7 4.7 COUT (F) 1410 2820 4700 1410 2820 4700 1410 2820 4700 RC (k) 6.8 15 22 18 43 62 43 91 150 CC (nF) 4.7 2.2 2.2 10 2.2 2.2 10 33 10 C1 (pF) 33 33 33 33 33 10 10 10 10
Table 4 shows the suggested compensation component values for 5V to 3.3V applications based on 1500F Sanyo MV-WX output capacitors.
Table 4. Recommended Compensation Network for 5V to 3.3V Applications Using Multiple Paralleled 1500F Sanyo MV-WX Output Capacitors
L1 (H) 1.2 1.2 1.2 2.4 2.4 2.4 4.7 4.7 4.7 COUT (F) 4500 6000 9000 4500 6000 9000 4500 6000 9000 RC (k) 22 30 39 51 62 82 100 150 200 CC (nF) 1.5 1 0.47 1 1 0.47 3.3 0.47 0.47 C1 (pF) 120 82 56 56 33 27 15 15 15
18
U
LAYOUT CONSIDERATIONS When laying out the printed circuit board, use the following checklist to ensure proper operation of the LTC3830. These items are also illustrated graphically in the layout diagram of Figure 11. The thicker lines show the high current paths. Note that at 10A current levels or above, current density in the PC board itself is a serious concern. Traces carrying high current should be as wide as possible. For example, a PCB fabricated with 2oz copper requires a minimum trace width of 0.15" to carry 10A. 1. In general, layout should begin with the location of the power devices. Be sure to orient the power circuitry so that a clean power flow path is achieved. Conductor widths should be maximized and lengths minimized. After you are satisfied with the power path, the control circuitry should be laid out. It is much easier to find routes for the relatively small traces in the control circuits than it is to find circuitous routes for high current paths. 2. The GND and PGND pins should be shorted directly at the LTC3830. This helps to minimize internal ground disturbances in the LTC3830 and prevent differences in ground potential from disrupting internal circuit operation. This connection should then tie into the ground plane at a single point, preferably at a fairly quiet point in the circuit such as close to the output capacitors. This is not always practical, however, due to physical constraints. Another reasonably good point to make this connection is between the output capacitors and the source connection of the bottom MOSFET Q2. Do not tie this single point ground in the trace run between the Q2 source and the input capacitor ground, as this area of the ground plane will be very noisy.
sn3830 3830fs
W
UU
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
3. The small-signal resistors and capacitors for frequency compensation and soft-start should be located very close to their respective pins and the ground ends connected to the signal ground pin through a separate trace. Do not connect these parts to the ground plane! 4. The VCC, PVCC1 and PVCC2 decoupling capacitors should be as close to the LTC3830 as possible. The 4.7F and 1F bypass capacitors shown at VCC, PVCC1 and PVCC2 will help provide optimum regulation performance.
100
+
4.7F 1F GND NC VCC PVCC2 PVCC1 LTC3830 FREQSET SHDN COMP C1 RC CC CSS GND SS G1 IMAX IFB SENSE + G2 FB SENSE - GND PGND NC PGND
Figure 11. Typical Schematic Showing Layout Considerations
U
5. The (+) plate of CIN should be connected as close as possible to the drain of the upper MOSFET, Q1. An additional 1F ceramic capacitor between VIN and power ground is recommended. 6. The SENSE and VFB pins are very sensitive to pickup from the switching node. Care should be taken to isolate SENSE and VFB from possible capacitive coupling to the inductor switching signal. Connecting the SENSE+ and SENSE - close to the load can significantly improve load regulation. 7. Kelvin sense IMAX and IFB at Q1's drain and source pins.
PVCC VIN 1F 0.1F Q1A 1k Q1B LO VOUT Q2
W
UU
+
CIN
+
COUT
PGND
3830 F11
sn3830 3830fs
19
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
5V
+
100 1F PVCC2 VCC 4.7F 0.1F 0.01F NC SHUTDOWN C1 33pF RC 18k CC 0.01F SS PVCC1 G1 IMAX LTC3830 IFB FREQSET SHDN COMP G2 PGND GND SENSE + SENSE- FB CIN: SANYO 6TPB330M COUT: SANYO 4TPB470M LO: SUMIDA CDEP105-2R5 Q1, Q2: VISHAY Si7892DP Q2 1k 0.1F LO 2.5H 6.8k 0.1F Q1
+
Figure 12. 5V to 3.3V, 10A Application
20
U
+
MBR0530T1 CIN 330F x2
W
UU
+
COUT 470F x3
3.3V 10A
3830 F012
sn3830 3830fs
LTC3830/LTC3830-1
PACKAGE DESCRIPTIO
.254 MIN
.0165 .0015
RECOMMENDED SOLDER PAD LAYOUT 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP .053 - .068 (1.351 - 1.727) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249)
U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005 .189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988) .0250 TYP .008 - .012 (0.203 - 0.305) .0250 (0.635) BSC
GN16 (SSOP) 0502
sn3830 3830fs
21
LTC3830/LTC3830-1
PACKAGE DESCRIPTIO
.050 BSC 8 N N .245 MIN .160 .005 .228 - .244 (5.791 - 6.197) 1 .030 .005 TYP 2 3 N/2
RECOMMENDED SOLDER PAD LAYOUT
.010 - .020 x 45 (0.254 - 0.508) .008 - .010 (0.203 - 0.254) 0- 8 TYP
.016 - .050 (0.406 - 1.270) NOTE: 1. DIMENSIONS IN
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
22
U
S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.045 .005 .189 - .197 (4.801 - 5.004) NOTE 3 7 6 5 .150 - .157 (3.810 - 3.988) NOTE 3 N/2 1 2 3 4 .053 - .069 (1.346 - 1.752) .004 - .010 (0.101 - 0.254) .014 - .019 (0.355 - 0.483) TYP .050 (1.270) BSC
SO8 0502
sn3830 3830fs
LTC3830/LTC3830-1
PACKAGE DESCRIPTIO
.050 BSC N 16 15 14
.245 MIN
1 .030 .005 TYP
2
3
N/2
RECOMMENDED SOLDER PAD LAYOUT 1 .010 - .020 x 45 (0.254 - 0.508) .053 - .069 (1.346 - 1.752) 0 - 8 TYP 2 3 4 5 6 7 8
.008 - .010 (0.203 - 0.254)
.016 - .050 (0.406 - 1.270) NOTE: 1. DIMENSIONS IN
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
S Package 16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.045 .005 .386 - .394 (9.804 - 10.008) NOTE 3 13 12 11 10 9 N .160 .005 .228 - .244 (5.791 - 6.197) N/2 .150 - .157 (3.810 - 3.988) NOTE 3 .004 - .010 (0.101 - 0.254) .014 - .019 (0.355 - 0.483) TYP .050 (1.270) BSC
S16 0502
sn3830 3830fs
23
LTC3830/LTC3830-1
TYPICAL APPLICATIO
100 4.7F
0.1F 0.01F
130k C1 33pF
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS LTC3830 is Pin-for-Pin Compatible and is Recommended for New Designs SO-8 with Current Limit. No RSENSETM required Constant Frequency, Standby 5V and 3.3V LDOs, 3.5V VIN 36V 550kHz, 25MHz GBW Voltage Mode, VIN 7V, No RSENSE Provides CPU Core, I/O and CLK Supplies for Portable Systems Current Mode, VIN to 36V, IOUT Up to 42A Fault Protection, Power Good, 3.5V to 36V Input, Current Mode Up to 95% Efficiency, 550kHz, 2.65V VIN 8.5V, 0.8V VOUT VIN, Synchronizable to 750kHz VIN Up to 36V, Current Mode, Power Good 1.3V to 3.5V Programmable Core Output Plus I/O Output Step-Down DC/DC Conversion from 3VIN, Minimum CIN and COUT, Uses Logic-Level N-Channel MOSFETs Current Mode Ensures Accurate Current Sensing VIN Up to 36V, IOUT Up to 40A Minimum VIN: 1.5V, Uses Standard Logic-Level N-Channel MOSFETs VOUT Tracks 1/2 of VIN or External Reference 0.6V VOUT 5V, Pin-for-Pin Compatible with the LTC3830 LTC1430/LTC1430A High Power Step-Down Switching Regulator Controllers LTC1530 LTC1628 LTC1702 LTC1705 LTC1709 LTC1736 LTC1773 LTC1778 LTC1873 LTC1876 LTC1929 LTC3713 LTC3831 LTC3832 High Power Synchronous Switching Regulator Controller Dual High Efficiency 2-Phase Synchronous Step-Down Controller Dual High Efficiency 2-Phase Synchronous Step-Down Controller Dual 550kHz Synchronous 2-Phase Switching Regulator Controller with 5-Bit VID Plus LDO 2-Phase, 5-Bit Desktop VID Synchronous Step-Down Controller Synchronous Step-Down Controller with 5-Bit Mobile VID Control Synchronous Step-Down Controller in MS10 Wide Operating Range/Step-Down Controller, No RSENSE Dual Synchronous Switching Regulator with 5-Bit Desktop VID 2-Phase, Dual Step-Down Synchronous Controller with Integrated Step-Up DC/DC Regulator 2-Phase, Synchronous High Efficiency Converter with Mobile VID Low Input Voltage, High Power, No RSENSE, Step-Down Synchronous Controller High Power Synchronous Switching Regulator Controller for DDR Memory Termination Synchronous Step-Down Controller
No RSENSE is a trademark of Linear Technology Corporation.
sn3830 3830fs
24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
Typical 3.3V to 2.5V, 14A Application
12V 3.3V CIN 330F x2
+
0.1F 10F 6.8k Q1 1k Q2 D1 LO 1.3H 2.5V 14A 16.5k 1% 16.9k 1%
PVCC2 VCC SS
PVCC1 G1 IMAX
LTC3830 IFB FREQSET G2 PGND GND SENSE + SENSE - NC FB NC
+
SHDN RC 18k CC 1500pF
SHDN COMP
COUT 470F x3
CIN: SANYO POSCAP 6TPB330M COUT: SANYO POSCAP 4TPB470M D1: MBRS330T3 LO: SUMIDA CDEP105-1R3 Q1, Q2: VISHAY Si7892DP
3830 TA01
LT/TP 0103 2K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2001

▲Up To Search▲

Price & Availability of LTC3830

	To Download LTC3830 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .